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ICS574 Zero Delay, Low Skew Buffer
Description
The ICS574 is a low jitter, low-skew, high performance PLL-based zero delay buffer for high speed applications. Based on ICS's proprietary low jitter Phase Locked Loop (PLL) techniques, the device provides four low skew outputs at speeds up to 160 MHz at 3.3 V. When one of the outputs is connected directly to FBIN, the rising edge of each output is aligned with the rising edge of the input clock. External delay elements connected in the feedback loops will cause the outputs to occur before the inputs by the amount of propagation delay of the external element. ICS manufactures the largest variety of clock generators and buffers, and is the largest clock supplier in the world.
Features
* Packaged in 8 pin narrow SOIC * Zero input-to-output delay * Four 1X outputs * Output to output skew is less than 150 ps * Output clocks up to 160 MHz at 3.3 V * External feedback path for output edge placement * Spread SmartTM technology works with spread spectrum clock generators * Full CMOS outputs with 18 mA output drive capability at TTL levels at 3.3 V * Advanced, low power, sub-micron CMOS process * Operating voltage from 3.0 to 5.5 V
Block Diagram
CLK1 FBIN CLKIN PLL CLK2 CLK3 CLK4
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Integrated Circuit Systems, Inc. * 525 Race Street * San Jose * CA * 95126 * (408)295-9800 * www.icst.com
ICS574 Zero Delay, Low Skew Buffer
Pin Assignment
CLKIN CLK1 CLK2 GND 1 2 3 4 8 7 6 5 FBIN CLK4 CLK3 VDD
Standard 8 pin SOIC
Pin Descriptions
Number 1 2, 3, 6, 7 5 4 8 Name CLKIN CLK1:4 VDD GND FBIN Type I O P P I Description Clock input. Connect to input clock source. Four clock outputs. Power supply. Connect both pins to same voltage (either 3.3V or 5V). Connect to ground. Feedback input.
Key: I = Input; O = output; P = power supply connection.
External Components
The ICS574 requires a minimum number of external components for proper operation. Decoupling capacitors of 0.1F should be connected between VDD and GND on pins 4 and 5, as close to the device as possible. A series termination resistor of 33 may be used close to the pin for each clock output to reduce reflections.
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Integrated Circuit Systems, Inc. * 525 Race Street * San Jose * CA * 95126 * (408)295-9800 * www.icst.com
ICS574 Zero Delay, Low Skew Buffer
Electrical Specifications
Parameter Conditions Minimum ABSOLUTE MAXIMUM RATINGS (note 1) Supply voltage, VDD Referenced to GND -0.5 Inputs and Clock Outputs Referenced to GND -0.5 Electrostatic Discharge MIL-STD-883 2000 Ambient Operating Temperature 0 Soldering Temperature Max of 10 seconds Junction temperature Storage temperature -65 DC CHARACTERISTICS (VDD = 3.3 V unless specified otherwise) Operating Voltage, VDD 3.00 Input High Voltage, VIH VDD/2+1 Input Low Voltage, VIL Output High Voltage, VOH IOH=-18 mA 2.4 Output Low Voltage, VOL IOL=18 mA Output High Voltage, VOH, CMOS level IOH=-5 mA VDD-0.4 Operating Supply Current, IDD (Note 2) No Load Short Circuit Current Each output Input Capacitance AC CHARACTERISTICS (VDD = 3.3 V unless specified otherwise) Input Clock Frequency FBIN to CLK1 20 Output Clock Frequency FBIN to CLK1 20 Output Clock Rise Time, CL=30pF 0.8 to 2.0V Output Clock Fall Time, CL=30pF 2.0 to 0.8V Output Clock Duty Cycle, VDD=3.3V At 1.4V 40 Device to Device Skew, equally loaded rising edges at VDD/2 Output to Output Skew, equally loaded rising edges at VDD/2 Maximum Absolute Jitter Cycle to Cycle Jitter, 30pF loads 66.67 MHz outputs Typical Maximum Units 7 VDD+0.5 70 260 150 150 5.50 VDD/2-1 0.4 36 65 7 160 160 1.5 1.5 60 700 150 250 V V V C C C C V V V V V V mA mA pF MHz MHz ns ns % ps ps ps ps
50
150
Notes: 1. Stresses beyond those listed under Absolute Maximum Ratings could cause permanent damage to the device. Prolonged exposure to levels above the operating limits but below the Absolute Maximums may affect device reliability. 2. With CLKIN = 160 MHz, FBIN to CLK4
Using Spread Spectrum Input Clocks
The ICS574 uses ICS' Spread Smart technology, allowing it to accurately track (pass through) any clocks that implement spread spectrum techniques.
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Integrated Circuit Systems, Inc. * 525 Race Street * San Jose * CA * 95126 * (408)295-9800 * www.icst.com
ICS574 Zero Delay, Low Skew Buffer
Package Outline and Package Dimensions (For current dimensional specifications, see JEDEC Publication No. 95.)
8 pin SOIC Inches Min Max 0.0532 0.0688 0.0040 0.0098 0.0130 0.0200 0.0075 0.0098 0.1890 0.1968 0.1497 0.1574 .050 BSC 0.2284 0.2440 0.0099 0.0195 0.0160 0.0500 Millimeters Min Max 1.35 1.75 0.10 0.24 0.33 0.51 0.19 0.24 4.80 5.00 3.80 4.00 1.27 BSC 5.80 6.20 0.25 0.50 0.41 1.27
E INDEX AREA
H
h x 45 D
Symbol A A1 B C D E e H h L
A1 e B
C
A L
Ordering Information Ordering Information Part/Order Number
ICS574M ICS574MT
Marking ICS574M ICS574M
Shipping packaging tubes tape and reel
Package 8 pin SOIC 8 pin SOIC
Temperature 0-70 C 0-70 C
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments.
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Revision 051801
Integrated Circuit Systems, Inc. * 525 Race Street * San Jose * CA * 95126 * (408)295-9800 * www.icst.com

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